C. Bohm, M. Engstrom, K. Jon-And, S. Hellman, S-O. Holmgren, E. Johansson, K. Prytz, N. Yamdagni, X. Zhao Department of Physics, University of Stockholm, S-113 85 Stockholm, Sweden R. Sundblad, S. Gustafsson, A. Cranesceu Sicon, Linkoping, Sweden P. Bodo, H. Hentzell LMC AB, Linkoping-Kista, Sweden
AbstractA design study and demonstrator program to achieve a compact solution to the first-level calorimeter trigger for the ATLAS detector will be described. The design has been tailored to fit the specific requirements of the chosen first- level trigger algorithms, taking advantage of modern system design methods and utilizing advanced system components. The latter include high-speed BiCMOS ASICs, MCMs and optical fibers for transmission of the input data. The computation task has been partitioned to obtain weakly interacting modules suitable for implementation in large custom-designed ASICs. The system topology is such that it allows a considerable flexibility for future modifications by redesigning a limited number of ASICs. In the ASIC layout phase special care has been taken to utilize inherent computation symmetries. This greatly simplifies layout and design verification as well as it later facilitates hardware tests.
The construction will use 4096 optical fibers to convey trigger-cell data from the hadron and electromagnetic calorimeter data at a rate of 800 Mb/s to the trigger processor. Here they are fanned out to their destinations via fiber splitters and entered into specially designed opto-electrical converters (using MCMs) located on the 16 processing boards. A major part of the computations are performed in dedicated processing ASICs. The merging of results from these circuits occur in a second type of custom-designed ASICs. Both types, however, will be implemented in a 0.5 m BiCMOS process. After being merged at the board level results are also merged on the system level so that they may be sent to the central trigger processor for the final decision. The use of bit-serial data representation for most of the calculations has led to a fast and compact design.
The project, which is part of the CERN based research and development activity RD-27, has now reached a point where the ASIC layout is under way, aiming at a first processing run in the late fall and preliminary tests during the spring 1996.
Christian Bohm Department of physics, University of Stockholm, Sweden Vanadisvagen 9 S-113 46 Stockholm BOHM@PHYSTO.SE +468164682 FAX +468347817