Hans Muller, Andre Bogaerts
CERN, Division ECP
AbstractThe international SCI standard is on its way to become the computer interconnect of the year 2000 for cost effective implementations of cluster computing and to provide very low latency to MPP systems. The PCI bus is a local bus extension, implemented in all major computer platforms as well in VMEbus as a self configuring system with hierarchical architecture. The eventbuilder layer for a millesium DAQ system can therefore be seen as a large data routing switch in between numerous local PCI segments on the front end units side and PCI or SCI interfaces on the CPU farm side. This paper describes our proposal for a scalable SCI DAQ system, based on PCI-SCI bridges, optical SCI links and multistage SCI switches. Advantages of using SCI and PCI are amongst others, transparent data access allowing to scale up to data rates and event sizes of LHC experiments with embedded flow control and event synchronisiation. First RD24 eventbuilding results are reported.
(Some Public References: IEEE/ANSI 1596 Standard, Convex Exemplar MPP system, Byte April 1995: article on P6 page 56, Nixdorf PCI-SCI Press release, SCIzzl association information on SCI via WWW http://sunrise.scu.edu/ Experiments at CERN 1994 ( grey book ) page 370,371 )
In a complementary way, the hierarchical PCI local bus is the de facto interface of all major computer platforms for local subsystems, local memory and video data. The VMEbus industry like other established bus manufacturers adopt the PMC mezzanine card environment with PCI protocol. This allows building simple crate interconnects via PCI, multiport access to data and provides a standard way to interface to embedded processors.
(References: PMC IEEE P1386 Draft, PCI-PCI bridge architecture, PCI Local Bus Spec 2.1 available via the SIG distributors, PCI'95 Proceedings St.Clara March 27-31, Available via 1995 Annabooks San Diego ISBN 0-929392-27-1, Fax: 619-673-1432 )
The architecture of large DAQ systems of the year 2000 and beyond can therefore be seen as a link-switch layer between PCI based DAQ front end units on one side and a CPU farm with PCI and/or SCI interface on the other side. This DAQ layer contains a large superswitch, being investigated by competing technologies and standards.
( References: Talks on SCI on DAQ conference at FNAL see http://www1.cern.ch/RD24/ slides of talk to ALICE Collaboration pages 12-16 of 8.6.95 http://sunshine.cern.ch:8080/DAQ/ PCI_ALICE.ps)
The SCI standard can naturally implement this switch in a uniform and cost effective way using a network of SCI ringlets and switches. The RD24 project is constructing a first DAQ demonstrator with PCI-SCI interface to VME, a first 4-ring by 4-ring SCI switch with up to 80 interconnected nodes by integration of SCI components from SCI industry callaborators in particular from Apple, Dolphin, IBM, and more.
The first eventbuilder skeleton tests yield very good figures beyond 25 kHz event rate for SUN stations, interconnected via SCI ringlets. Increasing speed of SCI components, today's availabilty of SCI switches and SCI's built-in scalabilty allow us predictions towards 100 kHz for 1 Mbyte events.
(Reference will be the RD24 Status report 1995, due 16 August 1995 and oral presentation to LCRB September 5, 1995)
Hans Muller CERN Division ECP Hans@sunshine.cern.ch Tel : +41 22 767 3533 Fax: +41 22 767 9355 Author: Dr. Hans Muller, CERN Div. ECP Co-Author: Dr. Andre Bogaerts, CERN Division ECP ( We are Co-spokesmen of RD24) Scope of paper: DAQ with in-trend computer industry standards Other: RD24 info: http://www1.cern.ch/RD24/ PCI-SCI info http://sunshine.cern.ch:8080/