Extending DART to meet the Data Acquisition Needs of Future Experiments at Fermilab

                   Abstract

While the initial implementation of DART has concentrated on providing working data acquisition systems for the (now eight) collaborating experiments in the next Fixed Target Run, the architecture and design of the system are such that the system can be extended to meet the requirements of a new round of experiments at Fermilab - such as those proposed for the Fermilab Main Injector era and beyond.

One of the challenges in the development of DART has been the need define an architecture - both in hardware and software - that provides a common yet cost effective solution for experiments from the small, 500 KBytes/sec throughput, to the large, 200 MBYtes/sec data collection rate; for DC and spill structured - where the spill might change - experiments; and for experiments which record all the data collected, to those who employ thousands of mips to reduce the data to be logged by factors of up to forty.

In this paper we explore ideas for extending these paradigms and architectures adopted to the requirements of the expected range of future experiments needs at Fermilab. We describe some of the concepts and implementations of the existing DART hardware and software architectures that make it a cost effective solution, suitable for extension to future technologies and experiment needs.

Additionally we will describe ongoing current R&D developments in the Computing Division that can be interfaced to and integrated with these architectures, in the areas of: high performance, parallel, programmable trigger processing; ATM and Fiber Channel switch networks; integration of and interface of online systems to centralized data storage and data analysis facilities; multiple on-detector ASICs which need downloading, control and monitoring.

Some of the areas we cover will include discussion of

a) the data collection and processing levels and layers.

The decoupling of the upper level hardware and software are from the front end readout scheme and number of "levels" of the data acquisition readout architecture. Event data is delivered to buffer memories up multiple parallel cables with minimal control - initial wordcount either in the data or pre-pended by a readout controller, or an End or Record strobe (EOR), and a BUSY return; Event data is readout and collected into sub-events or events from these buffer memories independently without the need to know the source of the data.

b) whether, when and how to build events.

Current DART experiments have no common definition of the "Event Builder". Each experiment has chosen the most efficient and effective point at which to finally tie together all the data from a single event - and it turns out that this is different from experiment to experiment.

Within DART there is a loose coupling between the level 3 event filter processors and the event collection system itself. This allows easy replacement by other event building and delivery paradigm. In the current implementation the event data is provided to level 3 filter processors independently over multiple VME crate backplanes and workstation-VME adaptors. The locally attached processors perform readout, processing and logging of sets of the events. Delivery of the data to filter processors through an alternative switch architecture can easily be accommodated.

c) distributed standard communication and control protocols and interfaces.

The DART control and communication architecture implements management and monitoring of arbitrarily connected, heterogenous, loosely-coupled systems. It supports integration of the needed slow control and monitoring sub-systems with the control of the main high speed data acquisition system, as well as the implementation of sub-systems for commissioning and testing with later integration to a orchestrated whole.