G. Ódor (1), F. Rohrbach (2), G. Vesztergombi (3), G. Varga, F. Tatrai (4) Institutes: (1) KFKI-ATKI, Budapest (H), (2) CERN, Geneva (CH), (3) KFKI-RMKI, Budapest (H), (4) Technical University, Budapest (H)
AbstractIn view of the tremendous computing power jump of modern RISC processors the interest in parallel computing seems to be thinning out. Why would one use a complicated system of parallel processors, if the problem could be solved by a single powerful microchip? It is a general law, however, that the exponential growth always will end by some kind of a saturation, and then the parallelism will become again a hot topic.
We try to prepare ourself for that eventuality. The MPPC project was started in 1990 in the hay-days of parallelism and produced four ASTRA machines (presented at CHEP'92) with 4k processors (which are expendable to 16k) based on "yesterday's chip-technology" (chip presented at CHEP'91).
Now these machines are providing excellent testbeds for algorithmic developments in a complete, real environment. We are developping e.g. fast pattern recognition algorithms which could be used in high energy physics experiments at LHC (planned to be operational after 2004 at CERN) for triggering and data reduction. The basic feature of our ASP (Associative String Processor) approach is to use extremly simple (thus very cheap) processor elements but in huge quantities (up to millions of processors) connected together by a very simple string-like communication chain.
In the paper we present powerful algorithms based on this architecture indicating the performance perspectives if the hardware ( i.e. chip fabrication) quality would reach the "present or even future technology level".